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CD40192BC * CD40193BC Synchronous 4-Bit Up/Down Decade Counter * Synchronous 4-Bit Up/Down Binary Counter
October 1987 Revised January 1999
CD40192BC * CD40193BC Synchronous 4-Bit Up/Down Decade Counter * Synchronous 4-Bit Up/Down Binary Counter
General Description
The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the other is clocked. The outputs change on the positive-going transition of this clock. These counters feature preset inputs that are enabled when load is a logical "0" and a clear which forces all outputs to "0" when it is at logical "1". The counters also have carry and borrow outputs so that they can be cascaded using no external circuitry. All inputs are protected against damage due to static discharge by clamps to VDD and VSS.
Features
s Wide supply voltage range: s High noise immunity: 3V to 15V 0.45 VDD (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s Carry and borrow outputs for easy expansion to N-bit by cascading s Asynchronous clear s Equivalent to: MM74C192 and MM74C193
Ordering Code:
Order Number CD40192BCN CD40193BCN CD40193BCM Package Number N16E N16E M16A Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Cascading Packages
Top View
(c) 1999 Fairchild Semiconductor Corporation
DS005988.prf
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CD40192BC * CD40193BC
Block Diagrams
CD40192BC Synchronous 4-Bit Up/Down Decade Counter
CD40193BC Synchronous 4-Bit Up/Down Binary Counter
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CD40192BC * CD40193BC
Absolute Maximum Ratings(Note 1)
(Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C (Note 3) 700 mW 500 mW -0.5 to +18 VDC -0.5 to VDD +0.5 VDC -65C to +150C
Recommended Operating Conditions (Note 2)
DC Supply Voltage (V DD) Input Voltage (VIN) Operating Temperature Range (TA) CD40192BC, CD40193BC -40C to +85C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The "Recommended Operating Conditions" and Electrical Characteristics tables provide conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.
3 to 15 VDC 0 to VDD VDC
DC Electrical Characteristics
Symbol IDD Parameter Quiescent Device Current VOL LOW Level Output Voltage VOH HIGH Level Output Voltage VIL LOW Level Input Voltage VIH HIGH Level Input Voltage IOL LOW Level Output Current (Note 4) IOH HIGH Level Output Current (Note 4) IIN Input Current
Conditions VDD = 5V, VIN = VDDor VSS VDD = 10V, VIN = VDD or VSS VDD = 15V, VIN = VDD or V SS VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, V IN = 15V
-40C Min Max 20 40 80 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.52 1.3 3.6 -0.52 -1.3 -3.6 -0.3 0.3 3.5 7.0 11.0 0.44 1.1 3.0 -0.44 -1.1 -3.0 4.95 9.95 14.95 Min
+25C Typ Max 20 40 80 0.05 0.05 0.05
+85C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 1.5 3.0 4.0
Units A A A V V V V V V V V V V V V mA mA mA mA mA mA
0.88 2.25 8.8 -0.88 -2.25 -8.8 -10-5 10-5 -0.3 0.3
0.36 0.9 2.4 -0.36 -0.9 -2.4 -1.0 1.0
A A
Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: IOH and IOL are tested one output at a time.
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CD40192BC * CD40193BC
AC Electrical Characteristics
Symbol tPHL or tPLH Parameter Propagation Delay Time from Count Up or Count Down to Q tPHL or tPLH Propagation Delay Time from Count Up to Carry tPHL or tPLH Propagation Delay Time from Count Down to Borrow tSU Time Prior to Load That Data Must Be Present tPHL Propagation Delay Time from Clear to Q tPLH or tPHL Propagation Delay Time from Load to Q tTLH or tTHL Output Transition Time
(Note 3)
Conditions Min Typ 250 100 80 120 50 40 120 50 40 100 30 25 130 60 50 300 120 95 100 50 40 2.5 6 7.5 15 5 1 120 35 28 300 120 95 100 40 32 5 10 100 200 80 65 480 190 150 160 65 55 7.5 15 4 10 12.5 Max 400 160 130 200 80 65 200 80 65 160 50 40 220 100 80 480 190 150 200 100 80 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz s s s ns ns ns ns ns ns ns ns ns pF pF pF
TA = 25C, CL = 50 pF, RL = 200 k, input tr = tf = 20 ns, unless otherwise specified. VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V fCL Maximum Count Frequency VDD = 5V VDD = 10V VDD = 15V trCL or t fCL Maximum Count Rise or Fall Time tWH, tWL Minimum Count Pulse Width tWH Minimum Clear Pulse Width tWL Minimum Load Pulse Width CIN Average Input Capacitance VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Load and Data Inputs (A,B,C,D) Count Up, Count Down and Clear CPD Power Dissipation Capacity (Note 5)
Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note, AN-90.
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CD40192BC * CD40193BC
Timing Diagrams
CD40192BC
Sequence: 1. Clear outputs to zero. 2. Load (preset) to BCD seven. 3. Count up to eight, nine, carry, zero, one and two. 4. Count down to one, zero, borrow, nine, eight and seven.
CD40193BC
Sequence: 1. Clear outputs to zero. 2. Load (preset) to binary thirteen. 3. Count up to fourteen, fifteen, carry, zero, one and two. 4. Count down to one, zero, borrow, fifteen, fourteen and thirteen.
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CD40192BC * CD40193BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body Package Number M16A
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CD40192BC * CD40193BC Synchronous 4-Bit Up/Down Decade Counter * Synchronous 4-Bit Up/Down Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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